A complementary metal-oxide-semiconductor (CMOS) circuit may operate as a switch, for example, to sample voltages that are received at an input. A typical CMOS circuit may be formed by an N-type metal-oxide-semiconductor (NMOS) transistor coupled in parallel with a P-type metal-oxide-semiconductor (PMOS) transistor, such that the NMOS transistor and PMOS transistor share a common input and a common output. The gates of the PMOS transistor and the NMOS transistor are controlled by complementary signals that may be used for activating or “turning on” the transistors. More specifically, when the transistors are turned on (e.g., when the enable signal is asserted), the CMOS switch allows the input to pass to the output. Thus, the output at any given time represents the voltage sampled on the input when the enable signal is asserted.
Analog CMOS switches typically exhibit poor supply rejection. Specifically, the output of a CMOS switch is susceptible to disturbances on a voltage supply line powering the CMOS circuitry. For example, a CMOS switch is typically activated when the gate of the NMOS transistor is coupled to a voltage supply line, which provides a relatively high “turn-on” voltage. However, parasitic capacitances between the gate and source (or drain) of the NMOS transistor may couple noise from the voltage supply line to the source terminal of the NMOS transistor, which may introduce voltage errors at the output of the CMOS switch. Thus, it may be desirable to reduce or minimize the coupling of noise from the voltage supply line to the output of the CMOS switch.